The present disclosure relates to semiconductor devices and methods for fabricating semiconductor devices, and more particularly to a semiconductor device having a complementary metal insulator semiconductor (CMIS) dual-gate structure and a method for fabricating such a semiconductor device.
The integration degree of semiconductor integrated circuits have been increased by miniaturizing CMIS devices with dual-gate structures. A CMIS device with a dual-gate structure generally refers to a device including a polysilicon film doped with an n-type impurity as a gate electrode of an n-channel metal insulator semiconductor field effect transistor (hereinafter referred to as an NMISFET) and also including a polysilicon film doped with a p-type impurity as a gate electrode of a p-channel MISFET (hereinafter referred to as a PMISFET) (see, for example, Japanese Patent Publication No. H06-275788). In a CMIS device with a dual-gate structure, a metal silicide layer is formed on a polysilicon gate electrode in order to connect an n-type polysilicon gate electrode and a p-type polysilicon gate electrode. In this structure, in the boundary between an n-type region and a p-type region in each of the polysilicon gate electrode, impurities in these regions are diffused from one region to the other through the metal silicide layer or the polysilicon film, resulting in a change in work function of the gate electrode, and thus, a variation in threshold voltage of each of the FETs.
As a conventional method for forming an n-type region and a p-type region in a polysilicon film for gate electrodes, ions of impurities are implanted into the polysilicon film for gate electrodes using a mask designed such that the boundary between the n-type region and the p-type region is located on an isolation between well regions (see, for example, Japanese Patent Publication No. H08-17934).
A conventional semiconductor device in which an n-type region and a p-type region are formed by implanting ions into gate electrodes of a transistor for a logic circuit and a transistor for a static random access memory (SRAM) circuit will be described with reference to the drawings.
FIG. 15A is a plan view illustrating a logic area of a conventional semiconductor device. FIG. 15B is a cross-sectional view taken along the line B-B (along the gate width) in FIG. 15A. FIG. 15C is a plan view illustrating an SRAM area of the conventional semiconductor device. FIG. 15D is a cross-sectional view taken along the line D-D (along the gate width) in FIG. 15C. In FIGS. 15A-15D, sidewall spacers, a silicide layer, and an interlayer film, for example, are not shown for simplicity, and contacts are not shown in FIGS. 15B and 15D.
As illustrated in FIGS. 15A-15D, each of the logic area and the SRAM area of the conventional semiconductor device has an NMIS region and a PMIS region. In the NMIS region in the logic area, a p-well region 102a is provided on a semiconductor substrate 100 and an active region 100a is surrounded by an isolation region 101. In the PMIS region in the logic area, an n-well region 102b is provided on the semiconductor substrate 100 and an active region 100b is surrounded by the isolation region 101. In the NMIS region in the SRAM area, a p-well region 102c is provided on the semiconductor substrate 100, and an active region 100c is surrounded by the isolation region 101. In the PMIS region in the SRAM area, an n-well region 102d is provided on the semiconductor substrate 100, and an active region 100d is surrounded by the isolation region 101.
On the active region 100a, a gate electrode 111a including an n-type polysilicon film 104a is formed with a gate insulating film 103 interposed therebetween. On the active region 100b, a gate electrode 111b including a p-type polysilicon film 104b is formed with the gate insulating film 103 interposed therebetween. The gate electrode 111a and the gate electrode 111b are connected to each other at a PN boundary 113L between the active region 100a and the active region 100b on the isolation region 101, thereby forming a dual-gate electrode 112L. N-type source/drain regions 105a are defined at both sides of the gate electrode 111a in the active region 100a. P-type source/drain regions 105b are defined at both sides of the gate electrode 111b in the active region 100b. A contact 108 is formed to be connected to the dual-gate electrode 112L, the n-type source/drain regions 105a, and the p-type source/drain regions 105b. 
On the active region 100c, a gate electrode 111c including an n-type polysilicon film 104c is formed with the gate insulating film 103 interposed therebetween. On the active region 100d, a gate electrode 111d including a p-type polysilicon film 104d is formed with gate insulating film 103 interposed therebetween. The gate electrode 111c and the gate electrode 111d are connected to each other at a PN boundary 1135 between the active region 100c and the active region 100d on the isolation region 101, thereby forming a dual-gate electrode 112S. N-type source/drain regions 105c are defined at both sides of the gate electrode 111c in the active region 100c. P-type source/drain regions 105d are defined at both sides of the gate electrode 111d in the active region 100d. A contact 108 is formed to be connected to the dual-gate electrode 112S, the n-type source/drain regions 105c, and the p-type source/drain regions 105d. 
FIGS. 16A and 16B are views schematically illustrating formation of a p-type region and an n-type region by implanting ions of impurities into a polysilicon film (before gate patterning) to be dual-gate electrodes 112L and 112S. In FIGS. 16A and 16B, components already shown in FIGS. 15A-15D are denoted by the same reference characters.
As illustrated in FIGS. 16A and 16B, in gate injection for the PMIS regions, ions of a p-type impurity are implanted into the polysilicon film 104 using a mask pattern 151 covering the NMIS region in each of the logic area and the SRAM area, thereby forming p-type polysilicon films 104b and 104d. That is, the p-type polysilicon films 104b and 104d have substantially the same concentration of the p-type impurity. In gate injection for the NMIS regions, ions of an n-type impurity are implanted into the polysilicon film 104 using a mask pattern 152 covering the PMIS region of each of the logic area and the SRAM area, thereby forming n-type polysilicon films 104a and 104c. That is, the n-type polysilicon films 104a and 104c have substantially the same concentration of the n-type impurity. For simplicity, not resist patterns actually employed in ion implantation but mask patterns on photomasks for forming the resist patterns are schematically shown as the mask patterns 151 and 152. The mask patterns 151 and 152 are designed such that the PN boundaries formed in the polysilicon film 104 are located between the active region 100a and the active region 100b and between the active region 100c and the active region 100d, respectively, on the isolation region 101.
Although not shown, in ion implantation for forming source/drain regions in each of the PMIS region and the NMIS region, mask patterns similar to the mask patterns 151 and 152 shown in FIGS. 16A and 16B are used.
In the gate injection illustrated in FIGS. 16A and 16B, the PN boundary formed in the polysilicon film 104 is located on a portion of the isolation region between the active regions. Thus, it is possible to reduce degradation of characteristics of FETs due to mutual diffusion of impurities between the n-type region and the p-type region in the polysilicon gate electrode.